Bipolar transistors are used in digital applications where the transistors must be capable of switching between different states very rapidly. Bipolar transistors also provide gain in high-frequency analog applications. Accordingly, the transistor cutoff frequency f.sub.T is an important parameter in designing a bipolar transistor for such a high-frequency digital or analog application. Cutoff frequency f.sub.T is the frequency at which the small-signal current gain drops to 1. Another important transistor design parameter is the collector saturation current I.sub.S per unit area.
Reducing transistor size in order to increase the number of bipolar transistors that can be packed in a given lateral area is a common transistor design objective. As the transistor lateral dimensions are scaled down, the vertical dimensions are also often scaled down, with the result that the base becomes thinner. In scaling down the base, both cutoff frequency f.sub.T and collector saturation current I.sub.S normally increase. This is advantageous.
In a simplified one-dimensional analysis, the increase in parameters f.sub.T and I.sub.S with decreasing metallurgical base thickness t.sub.B can be seen from the following equations that apply to a single-emitter npn transistor: ##EQU1## where:
.alpha..sub.O is the static common-base current gain (nearly 1),
D.sub.n is the average electron diffusivity in the base,
t.sub.BEFF is the effective electrical thickness of the base--i.e., the distance between the boundaries of the emitter-base and collector-base depletion regions,
q is the electronic charge,
n.sub.i is the intrinsic electron density (approximately 1.4.times.10.sup.10 electrons/cm.sup.3 in silicon at room temperature),
N.sub.A is the base (acceptor) dopant concentration, and
x is an integrating variable in the base along the direction of main current flow.
Effective base thickness t.sub.BEFF decreases as metallurgical base thickness t.sub.B --i.e., the distance between the emitter-base and collector-base junctions--decreases. Since t.sub.BEFF is in the denominator of Eq. 1, cutoff frequency f.sub.T increases with decreasing t.sub.BEFF. Use of t.sub.BEFF in the dopant integral of Eq. 2 indicates that this integral, commonly referred to as the base Gummel number, is taken across the quasi-neutral region of the base--i.e., the region extending between the two depletion regions. The base Gummel number generally decreases as t.sub.BEFF, and thus t.sub.B, decrease. As a result, collector saturation current I.sub.S increases with decreasing t.sub.B.
The collector current I.sub.C per unit area is determined from saturation current I.sub.S according to the following approximate relationship: EQU I.sub.C =I.sub.S exp (q V.sub.BE /k T) (3)
where:
V.sub.BE is the base-to-emitter voltage,
k is Boltzmann's constant, and
T is the absolute temperature.
Since saturation current I.sub.S increases with decreasing base thickness t.sub.B, collector current I.sub.C advantageously increases as t.sub.B is down-scaled.
The current gain .beta. is also an important factor in designing a high-frequency bipolar transistor. Current gain .beta. is defined as I.sub.C /I.sub.B where I.sub.B is the base current per unit area. For highly simplified conditions (i.e., uniform, abrupt-junction dopant profiles with ideal emitter efficiency), current gain .beta. is given approximately as: ##EQU2## where L.sub.n is the minority carrier diffusion length in the base. Although Eq. 4 is a rough approximation, it reflects the fact that .beta. increases as metallurgical base thickness t.sub.B is reduced. The net result is that parameters f.sub.T, I.sub.S, I.sub.C, and .beta. all increase when the base is made thinner.
Eqs. 1-4 are available in prior art semiconductor literature. See: Philips, Transistor Engineering (McGraw-Hill; reprinted: Robert E. Krieger Pub. Co., 1981), 1962, pages 298-304; Warner et al, Transistor Fundamentals for the Integrated-Circuit Engineer (John Wiley & Sons), 1983, pages 559-562; and Grove, Physics and Technology of Semiconductor Devices (John Wiley & Sons), 1967, pages 219-222.
In a vertical bipolar transistor, the emitter adjoins a surface, referred to here as the upper surface, of a semiconductor body. The base consists of an intrinsic part (commonly termed the "intrinsic base") and one or more laterally adjoining extrinsic parts (commonly termed "extrinsic bases"). The intrinsic base lies directly below the emitter. Each extrinsic base includes a heavily doped base contact zone which extends to the upper surface of the semiconductor body and to which electrical contact is made at a location spaced laterally apart from the emitter.
The collector typically includes a lightly to moderately doped main collector region situated directly below the intrinsic base. The collector further includes a heavily doped buried layer that lies below the main collector region and extends laterally beyond the intrinsic base to a heavily doped collector contact zone which typically extends to the upper semiconductor surface to provide electrical access to the collector. Overlying electrical contacts to the emitter and to the contact zones complete the basic transistor. Additionally, a field-isolation region typically surrounds the emitter and base to separate the base from the collector contact zone and from other device elements in the semiconductor body.
The field-isolation region in many high-frequency bipolar transistors is formed with electrically insulating material, typically silicon oxide, whose sidewalls terminate the base. As used here, "terminate" means that the terminated item extends to the item which performs the termination. FIGS. 1a and 1b, which are taken at vertical cross sections perpendicular to each other, illustrate a typical prior art npn transistor whose base is terminated at an oxide-isolation region of the LOCOS type. For example, see Alvarez, BiCMOS Technology and Applications (Kluwer Acad. Pub., 2d ed.), 1993, pages 96-100, in regard to the cross section of FIG. 1a.
The transistor in FIGS. 1a and 1b is fabricated from a semiconductor body consisting of p-silicon substrate 20 and overlying n-silicon epitaxial layer 22. N+buried collector layer 24 lies along the metallurgical interface between substrate 20 and epitaxial layer 22. Field oxide 26 serves as the oxide-isolation region. N+emitter 28 is created in a self-aligned manner by out-diffusion from n+emitter contact 30. The remaining transistor elements are p-base layer 32, a pair of p+base contact zones 34, n-main collector region 36, and n+collector contact zone 38. The intrinsic base consists of the portion of base layer 32 underlying emitter 30.
In transistor structures of the foregoing type, the emitter is typically configured as a finger (or stripe) which is terminated at both ends by sidewalls of the field-isolation region. See FIG. 1b. This configuration is referred to here as a "walled-emitter" structure. Walled-emitter transistors are advantageous because they make highly efficient use of the active area. The parasitic collector-base capacitance is quite low for a given active area, thereby improving performance.
Ratnam et al, "The Effect of Isolation Edge Profile on the Leakage and Breakdown Characteristics of Advanced Bipolar Transistors," IEEE Bipolar Cirs. & Tech. Meeting, 7-8 Oct. 1992, pages 117-120, deals with walled-emitter bipolar transistors. Ratnam et al observed that the emitter termination regions of a walled-emitter vertical bipolar transistor typically cannot accommodate the same degree of down-scaling as the intrinsic transistor region without adversely affecting the collector-to-emitter leakage current and the collector-to-emitter breakdown voltage of the entire transistor. In particular, the high values of local current gain that can be obtained by vertically down-scaling the intrinsic base are not desirable at the emitter termination regions where two-dimensional doping effects can readily cause premature collector-to-emitter avalanche breakdown to occur.
The influence of the emitter termination regions on collector-to-emitter leakage current and breakdown voltage is difficult to express in simple first-order equations because of the two-dimensional nature of the dopant profiles in the termination regions. Nonetheless, a rough approximation of breakdown voltage BV.sub.CEO and the collector-to-emitter leakage current I.sub.CEO per unit area can be obtained from the following equations: ##EQU3## where:
I.sub.CBO is the leakage current per unit area of the collector-base junction,
BV.sub.CBO is the breakdown voltage of the collector-base junction,
n, typically in the range of 4-8, is an empirically determined coefficient,
X.sub.CB is the thickness of the collector-base depletion region at a given value of collector-to-emitter voltage V.sub.CE, and
.tau..sub.O is the carrier generation lifetime in the vicinity of the collector-base junction.
As with Eqs. 1-4, Eqs. 5 and 6 are available in prior art semiconductor literature. See: Grove, cited above, pages 230-234; and Muller et al, Device Electronics for Integrated Circuits (John Wiley & Sons), 1977, pages 174-179.
Leakage current I.sub.CBO approaches infinity at a value of collector-to-emitter voltage V.sub.CE equal to collector-to-emitter breakdown voltage BV.sub.CEO. Accordingly: ##EQU4##
Eqs. 5-7 can be separately applied to the intrinsic and emitter-termination regions of the transistor. Regardless of how accurate Eqs. 5-7 are, they reflect the fact that high local values of current gain .beta. caused by down-scaling the intrinsic base or by two-dimensional doping effects reduce breakdown voltage BV.sub.CEO and increase leakage current I.sub.CEO. Such two-dimensional effects occur in advanced BiCMOS processes where the intrinsic base is doped from overlying polysilicon as observed in Ratnam et al, cited above.
Ratnam et al also observed that the two-dimensional doping effects are strongly dependent on the slope of the isolation-oxide sidewalls, especially those having the "bird's beak" shape characteristic of fabrication processes in which the field-isolation region consists primarily of thermally grown silicon oxide. This dependency can be attributed to the combined effects of (a) impurity segregation into the oxide-isolation region and (b) base diffusion blocking by the "bird's beak" portion of the isolation oxide. It would be desirable to reduce current gain .beta. at the emitter termination regions so as to preserve or increase breakdown voltage BV.sub.CEO for the entire transistor.
Independent of avalanche-caused collector-to-emitter breakdown, down-scaling of the intrinsic base can cause punch-through to occur at the emitter termination regions. At punch-through, the depletion region of the collector-base junction reaches the depletion region of the emitter-base junction so as to eliminate the normally intervening quasi-neutral base region in which diffusion limits the current flow. The number of electrons passing through the base thereby increases rapidly in a generally undesirable manner as collector-to-emitter voltage V.sub.CE is increased. Breakdown voltage BV.sub.CEO is again impaired.
Ratnam, U.S. Pat. No. 5,338,695, describes a technique for improving parameters BV.sub.CEO and I.sub.CEO in a walled-emitter vertical bipolar transistor. The edges of the intrinsic base below the emitter termination regions are selectively provided with additional base dopant, typically by outdiffusion from overlying polysilicon. The thickness of the intrinsic base is thereby increased below the emitter termination regions. This typically produces an increase in breakdown voltage V.sub.CEO and a decrease in leakage current I.sub.CEO. While Ratnam mentions the transistor current gain and the cutoff frequency f.sub.T, Ratnam does not actively address improving these parameters.
Konaka et al, "A 20 ps/G Si Bipolar IC Using Advanced SST with Collector Ion Implantation," Procs. Solid State Devs. & Mats. Conf., 1987, pages 331-334, describes a vertical bipolar transistor that utilizes a selective collector implant to improve cutoff frequency f.sub.T and the maximum collector current density. FIG. 2 illustrates part of the transistor in Konaka et al. The transistor includes p-silicon semiconductor substrate 40, overlying n-epitaxial silicon collector portion 42, buried n+collector layer 44 along the substrate/epi interface, and field-isolation region 46 of the trench type. N+polysilicon emitter contact 48 contacts n+emitter 50 in a self-aligned manner. The transistor further includes p base layer 52, a pair of laterally separated p base contact zones 54, and p+polysilicon base contact 56.
Konaka et al performs a selective ion implantation to increase the net collector doping below the emitter and intrinsic base. Item 58 in FIG. 2 is the resulting selectively ion-implanted collector ("SIC") zone. The increased collector doping in SIC zone 58 shallows up the base thickness beyond the limits imposed by the base ion-implantation profile. SIC collector zone 58 causes the base push-out (Kirk) effect to occur at a higher value of the collector current density. The maximum collector-current density thus occurs at a greater value of cutoff frequency f.sub.T. Metallurgical base thickness t.sub.S decreases as the doping level of collector zone 58 increases. Reducing the base thickness and the base push-out effect thereby improves the cutoff frequency f.sub.T and the maximum collector-current density.
In the cross section of FIG. 2, emitter 50 does not terminate at the sidewalls of field-isolation region 46. Konaka et al does not provide a vertical device cross section perpendicular to the cross section of FIG. 2. Nonetheless, Konaka et al employs a double-polysilicon self-aligned fabrication process which is generally understood to produce bipolar transistors whose emitters do not terminate at the isolation-oxide sidewalls. Although Konaka et al can improve cutoff frequency f.sub.T, their utilization of the active transistor area is relatively inefficient. It is desirable to have a bipolar transistor that efficiently utilizes the active area while improving cutoff frequency f.sub.T, the overall transistor current gain, breakdown voltage BV.sub.CEO, and leakage current I.sub.CEO.